The invention relates generally to integrated circuits and, in particular, to device structures for a field-effect transistor with a strained channel and methods of forming such device structures.
Complementary metal-oxide-semiconductor (CMOS) technology is used in microprocessors, static random access memories, and other types of digital integrated circuits. Generally, CMOS technology relies on complementary and symmetrical pairs of p-type and n-type field-effect transistors (nFETs and pFETS) to implement logic functions. Planar field-effect transistors include an active semiconductor region, a source and a drain defined in the active semiconductor region, and a gate electrode. When a control voltage exceeding a characteristic threshold voltage is applied to the gate electrode, an inversion or depletion layer is formed in a channel defined in the active semiconductor region between the source and drain by the resultant electric field and carrier flow occurs between the source and drain to produce a device output current.
Semiconductor-on-insulator (SOI) substrates may be advantageous in CMOS technology. In comparison with field-effect transistors built using a bulk silicon wafer, a semiconductor-on-insulator substrate permits operation at significantly higher speeds with improved electrical isolation and reduced electrical losses. The performance of field-effect transistors may be improved through the use of thin active semiconductor layers, which permit the field-effect transistors to operate in a fully-depleted state in which the depletion layer extends to the buried oxide layer when typical control voltages are applied to the gate electrode.
In certain technology nodes, different channel materials may be used for n-type field-effect transistor and p-type field-effect transistor devices. For example, the device performance of a p-type field-effect transistor may be enhanced if the channel is composed of a different semiconductor material than silicon. For example, the channel of a p-type field-effect transistor may be composed of silicon germanium (SiGe), which is characterized by a higher hole carrier mobility that is greater than the hole mobility of silicon.
Shallow trench isolation (STI) is a used in semiconductor fabrication for isolating neighboring field-effect transistors. Shallow trench isolation is formed by etching trenches that circumscribe an active semiconductor region and filling the trenches with an electrical insulator, such as silicon dioxide. Under certain circumstances, the shallow trench isolation may unwantedly relax the strain that is present in the SiGe channel of a p-type field-effect transistor.
Improved device structures for a field-effect transistor with a strained channel and methods of forming such device structures are needed.